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General Resume

NameXuan Wu (pronounced Shuen Wu)
Address307 College Ave., Palo Alto, CA 94306
E-mailxuanwu@stanford.edu
CitizenshipUSA

Education

Sept 2008 - PresentStanford University, Ph. D. (GPA: 4.21)
Electrical Engineering, focus on Research
Expected graduation date: 2099

Sept 2006 - March 2008Stanford University, M. S. (GPA: 4.04)
Electrical Engineering, focus on Lasers, Optoelectronics, and Quantum Electronics
GRE: 800/800 Math, 720/800 Verbal, 5.5/6.0 Analytic

Sept 2002 - June 2006Stanford University, B. S. (GPA: 3.81)
Electrical Engineering, focus on Solid State Electronics and Photonics
Computer Science minor
SAT: 1590/1600 General, 800/800 Math IIC, 800/800 Physics, 800/800 Writing

June 2001 - June 2002UC Riverside. (GPA: 4.3)
Summer Academy for high school students and High School-University Program during the school year (one college class per quarter)

CourseworkQuantum mechanics, lasers, nanophotonics and metamaterials, optical communications, nonlinear optics

LabworkVerilog hardware programming, mechatronics, analog communications, wireless RF, optics/photonics

Experience

June 2009 - Sept 2009Advanced Development Intern, Symmetricom Inc., San Jose, CA
Ported code from a wide array of projects from other products onto the Freescale MPC8313 platform.

Sept 2008 - Dec 2008Teaching Assistant, Stanford, CA
TA for Applied Quantum Mechanics I (EE222) in a class of 75 students. Gave review sessions, helped students on homework, gave a few lectures, and graded major assignment, midterm, and final.

June 2008 - Sept 2008Advanced Development Intern, Symmetricom Inc., San Jose, CA
Ported Internet Protocol Performance Metrics (IPPM) applications onto a Blade. Worked with application-level code and driver-level code. Ran network tests to evaluate Blade performance.

Jan 2008 - March 2008
Jan 2007 - March 2007
Teaching Assistant, Stanford, CA
TA for Analog Communications Lab (EE133), an RF project-based course. Supervised lab hours, edited handouts for prelabs and labs, graded reports, answered questions, and helped students debug circuits.

June 2007 - Sept 2007Design Engineer Intern, Intersil Corporation, Milpitas, CA
Worked on a proof-of-concept digital isolator from initial design to tapeout. Performed EM simulation using Ansoft HFSS, built lumped models, designed and simulated circuits using Cadence Virtuoso and Spectre, and wrote documentation.

Additional Information

SkillsFluency in Chinese, typesetting in LaTeX
InterestsTheology, piano, drawing, tennis, table tennis, badminton, graphics design, learning languages, game programming, weightlifting, cooking